|Title:||Hardware mapping of a parallel algorithm for matrix-vector multiplication overlapping communications and computations||Authors:||Ojeda-Guerra, C. N.
|UNESCO Clasification:||3325 Tecnología de las telecomunicaciones||Keywords:||algorithm
|Issue Date:||1998||Journal:||Lecture Notes in Computer Science||Conference:||8th International Workshop on Field-Programmable Logic and Applications, FPL 1998||Abstract:||The parallelization of numerical algorithms is very important in scientific applications, but many points of this parallelization remain open today. Specifically, the overhead introduced by loading and unloading the data degrades the efficiency, and in a realistic approach should be taking into account for performance estimation. The authors of this paper present a way of overcoming the bottleneck of loading and unloading the data by overlapping computations and communications in a specific algorithm such as matrix-vector multiplication. Also, a way of mapping this algorithm in hardware is presented in order to demonstrate the parallelization methodology.||URI:||http://hdl.handle.net/10553/48188||ISBN:||3540649484||ISSN:||0302-9743||Source:||Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)[ISSN 0302-9743],v. 1482, p. 396-400|
|Appears in Collections:||Actas de congresos|
checked on Dec 3, 2023
checked on Jun 24, 2023
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.